Circuit for detecting a change in voltage level in either sense

ABSTRACT

First and second cross-coupled logic gates respectively connected to third and fourth logic gates, with feedback connections from the third to the second and the fourth to the first gate. The input voltage level whose change in value it is desired to sense is applied to the third gate and its complement is applied to the second and fourth gates. When this input voltage changes its value in one sense, an output pulse is produced by the third gate and when it changes its value in the opposite sense, an output pulse is produced by the fourth gate. The logic gates may be NAND or NOR gates.

United States Patent Donald John Barth Bedford, Mss. 845,855

July 29, 1969 Apr. 20, 1971 RCA Corporation Inventor Appl. No. Filed Patented Assignee CIRCUIT FOR DETECTING A CHANGE IN VOLTAGE LEVEL IN EITHER SENSE 291, 218 (LlT.); 328/206, 118; 307/236 Assistant Examiner-David M. Carter Attorney-H. Christofiersen ABSTRACT: First and second cross-coupled logic gates respectively connected to third and fourth logic gates, with feedback connections from the third to the second and the fourth to the first gate. The input voltage level whose change in value it is desired to sense is applied to the third gate and its complement is applied to the second and fourth gates. When this input voltage changes its value in one sense, an output pulse is produced by the third gate and when it changes its value in the opposite sense, an output pulse is produced by the fourth gate. The logic gates may be NAND or NOR gates.

PATENIE0APR20|97| 3575.608

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PATENTFUAPMOISYI 3575.608 'SHEET 2 OF 2 INVEN'TOR.

ATTORNEY CIRCUIT FOR DETECTING A CHANGE IN VOLTAGE LEVEL IN EITHER SENSE BACKGROUND OF THE INVENTION SUMMARY or THE INVENTION The circuit of the invention includes first and second crosscoupled logic gates respectively connected to third and fourth logic gates. The output of the third gate is, applied to the second gate and the output of the fourth gate to the first gate. The voltage level being monitoredis applied to the third gate and its complement is applied to the second and fourth gates.

BRIEF DESCRIPTION OF THE DRAWING.

FIG. 1 is a logic diagram of one form of the invention;

FIG. 2 is a drawing of waveforms to explain the operation of the circuit of FIG. 1; and

FIG. 3 is a logic diagram of a second form of the present invention.

DETAILED DESCRIPTION The circuit of the present invention may be constructed with NAfiD gates. Such a gate implements the Boolean equation Z=XY=X+ Y The truth table for a NAND gate is X Y Z The circuit of FIG. 1 includes an inverter 8 and five NAND gates l0, l2, l4, l6 and 18. The first and second NAND gates,

10 and 12 are cross-coupled. The output signal. D of the first NAND gate 10 is applied to the third NAND gate 14 and the output signal E of the second NAND gate 12 is applied to the fourth NAND gate 16. The output signal A of the third NAND gate 14 is fed back to the second NAND gate. 12 and the output signal C of the fourth NAND gate 16 is fed back to the first NAND gate 10. The signals A and C are applied to the fifth NAND gate 18. The voltage level P, which is the input level being monitored, is applied to the third NANDgate I4. and its complement P is applied to the second and fourth NAND gates 12 and 16.

In the operation of the circuit of FIG. I, assume that? inigally is a relatively low voltage level representing the bit 0 and P is a relatively high voltage level representing the bit 1. Analysis of the circuit under these conditions will show that A, D andC are all high voltage levels representing a 1 and E and B relatively low voltage levels representing a 0, all as shown in- FIG. 2. (hereafter, rather than referring to voltage levels, reference will be made to the binary digits which are represented by voltage levels).

FIGS. 1 and 2 should now be referredto. In the latter, each interval from t, to t,,,., and from t to t ,tone gate delay interval. At time t P changes from 0 to 1. One gate delay interval later at time t,, inverter 8 produces an output P=0. At this same time t,, gate 14 produces an output-A==0, astime t, is one gate delay interval after P has changed to l (the second input D to gate 14 already is l One gate delay intervalafter A changes to 0, that is, at time E changes to l. The reason is. that A=0 is an'input to NAND gate 12 and the latter produces a 1 output when any one or more of itsinputs is a 0.

At time t C has the value 1. Therefore, the two inputs to NAND gate 10 are 1, so that one gate delay interval later, that is, at time 1 D changes to 0. One gate delay interval later, at time t,,, the output of gate 14 changes back to its original value A=l. Thus, a negative pulse has been produced at A which is three gate delay intervals in duration.

Assume now that at some later time t P changes its value from 1 back to 0. One gate delay interval later at time inverter 8 produces an output P=l One gate delay interval later, at time t gate 16 produces anoutput C=0 as its two inputs both are 1. One gate delay interval later, at time D the output of NAND gate 10, changes to l as C is 0. One gate delay interval later, at time E changes to 0 as the three inputs to NAND gate 12, that is, D, P and A are all 1. One gate delay interval later, at time 2 C changes back to l as E now is The inputs A and C applied to NAND gate 18 cause this NAND gate to produce the output pulses B. These pulses are relatively positive (represent the bit 1) and a pulse B is produced one gate delay interval after the production of a pulse A or a pulse C as shown in FIG. 2. While not shown, it is to be understood that inverts may be employed to convert the relatively negative pulses A and C to relatively positive pulses, if desired. It is also to be understood that a NAND gate may be employed rather than inverter 8 if it is desired to use all identical logic gates in the circuit.

A second implementation of the present invention is shown in FIG. 3. It includes 4 NOR gates 10a, 12a, 14a and 16a connected in the same way as the NAND gates l0, l2, l4 and 16 of FIG. 1. A NOR gate implements the Boolean equation Z= X Y'= Y 7. The truth table for a NOR gate is In addition to theNOR gates, the circuit of FIG. 3 includes an inverter 8a corresponding to the inverter 8 of FIG. 1. The circuit also includes an OR gate connected to receive the outputs A and C of NOR gates 14a and 16a respectively.

The operation of the circuit of FIG. 3 is quite similar to that of thecircuit of FIG. 1. However, the NOR gates 14a and 16a produce pulses representing the bit 1 rather than the pulses representing the bit 0 produced by the circuit of FIG. 1. In addition, the OR gate 18a also produces a pulse representing a 1 whenever either A=1 or C==1.

The operation of the circuit of FIG. 3 is fully described in the truth table which follows:

is t; in

I claim: I. A circuit for detecting a change in voltage level in either sense comprising, in combination:

first and second cross-coupled logic gates;

a third logic gate connected to receive the output of the first logic gate;

a fourth logic gate connected toreceive the output of the second logic gate;

a feedback connection from the output of the third logic gate to the second logic gate;

a feedback connection from the output of the fourth logic gate to the first logic gate; and

means for applying the voltage whose level is being sensed and which is indicative of a binary digit of one value to said third logic gate and a complementary voltage level indicative of the binary digit of other value to the second and fourth gates.

2. In the combination set forth in claim 1 said four gates comprising four NAND gates.

3. In the combination set forth in claim 1 said four gates comprising four NOR gates. 

1. A circuit for detecting a change in voltage level in either sense comprising, in combination: first and second cross-coupled logic gates; a third logic gate connected to receive the output of the first logic gate; a fourth logic gate connected to receive the output of the second logic gate; a feedback connection from the output of the third logic gate to the second logic gate; a feedback connection from the output of the fourth logiC gate to the first logic gate; and means for applying the voltage whose level is being sensed and which is indicative of a binary digit of one value to said third logic gate and a complementary voltage level indicative of the binary digit of other value to the second and fourth gates.
 2. In the combination set forth in claim 1 said four gates comprising four NAND gates.
 3. In the combination set forth in claim 1 said four gates comprising four NOR gates.
 4. In the combination set forth in claim 1 a fifth gate coupled to said third and fourth gates for producing an output pulse when either the third or fourth gate produces an output pulse. 